QDR II SRAM for high-throughput buffering
The CY7C1314CV18-250BZC is a 18 Mbit QDR II synchronous SRAM organized as 512K x 36, clocked at 250 MHz. The QDR II architecture provides separate read and write data ports, eliminating bus-turnaround cycles and sustaining full-rate throughput in packet-processing and cache applications. Operating from a 1.7 V to 1.9 V core supply, it is a volatile SRAM in a 165-ball LBGA (13x15 mm FBGA) package, surface-mount.
Infineon lists this part as Obsolete. No official successor is recorded in the ledger. The 165-FBGA package (13x15 mm) and 250 MHz speed grade are the key constraints for a pin-compatible substitute. Any replacement candidate must match the QDR II interface, 1.8 V supply, and the same footprint to avoid a board respin.