18 Mbit QDR II SRAM at 250 MHz — the bus-margin decision
The CY7C1313KV18-250BZCT is a QDR II (Quad Data Rate II) synchronous SRAM from Infineon (formerly Cypress), organized 1M x 18 for a total of 18 Mbit. It clocks at 250 MHz, delivering four data words per clock cycle on separate read and write ports — a bus architecture that eliminates the dead cycles of common-I/O SRAM. The 1.7V to 1.9V supply rail and 165-ball FBGA package (13x15 mm) target networking and telecom line cards where the packet buffer or lookup table must keep up with a 250 MHz FPGA or network processor without wait states.
250 MHz clock — what it buys the timing budget
At 250 MHz the QDR II interface delivers a 500 MHz effective data rate on each port (double data rate on the clock edges), so the memory can sustain back-to-back reads and writes at the full clock rate. The 1M x 18 organization means the controller sees an 18-bit wide data bus per port; a 36-bit wide word requires two devices in parallel.
Package and supply — footprint and rail check
The 165-ball FBGA (13x15 mm) is a fine-pitch BGA; the board requires microvias and a clean 1.8V rail within 5% tolerance. The base product number CY7C1313 covers both variants, so the pinout and footprint are identical; only the shipping medium differs.
Infineon lists this part as Active.