18 Mbit QDR II at 200 MHz — the line-rate ceiling
The CY7C1313CV18-200BZXI is a 18 Mbit QDR II SRAM organized 1M x 18, clocked at 200 MHz. At this speed, the read and write ports each deliver 400 MB/s of theoretical bandwidth — the limiting factor in a backplane or line-card buffer is the FPGA or ASIC interface timing, not the memory itself. Supply voltage is 1.7V to 1.9V, so a single 1.8V rail with ±100 mV tolerance powers the core — no separate VDDQ. The parallel interface uses separate read and write data buses, which doubles throughput per clock cycle compared to a common-I/O SRAM.
Industrial temp and FBGA footprint
The package ships in Tray format, which is standard for low-volume production and prototyping — no reel fee or tape-and-reel minimum to absorb.
Infineon lists the CY7C1313CV18-200BZXI as Obsolete. For a BOM that already carries this part number, the procurement decision is whether to secure a last-time-buy quantity or qualify a functional replacement. The 165-FBGA footprint and 1.8V core are common across the QDR II family, but a direct drop-in without a board spin is not guaranteed.