It clocks at 300 MHz, delivering back-to-back read and write transactions on every rising and falling edge without dead cycles between bus-turnarounds — the defining advantage of the QDR II architecture over standard NoBL or DDR SRAMs. This part targets high-throughput packet buffering in networking equipment, FPGA cache, and test-and-measurement capture buffers where sustained bandwidth matters more than latency.
The ball map is specific to the 1M x 18 organization — verify against the footprint in the datasheet before committing the PCB layout. No exposed thermal pad; junction-to-board thermal path relies on the BGA balls and any via array under the package.
Temperature grade — indoor only
If the design requires -40°C to 85°C or wider, look at the industrial-temperature suffix variants in the QDR II family — the pin-compatible -300BZI or -300BZXI versions carry the same 300 MHz speed grade but with the extended temperature range.