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Infineon Technologies CY7C1308DV25C-167BZCT — Memory (DRAM / SRAM / Flash / EEPROM)

CY7C1308DV25C-167BZCT Infineon 9Mbit DDR SRAM, 167 MHz

MPNCY7C1308DV25C-167BZCT
Obsolete

Infineon Technologies CY7C1308DV25C-167BZCT DDR SRAM, Synchronous, 9Mbit, 256K x 36, 167 MHz, 2.4V-2.6V, 165-LBGA, Tape & Reel.

$21.7500Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

CY7C1308DV25C-167BZCT specifications
ParameterValue
Memory typeVolatile
MountingSurface Mount
Supply voltage2.4V ~ 2.6V
Clock frequency167 MHz
Memory interfaceParallel
Operating temperature0°C~70°C(TA)
PackageTape & Reel (TR)
TechnologySRAM - Synchronous, DDR
Memory size9Mbit
Memory formatSRAM
Case165-LBGA
Memory organization256K x 36

Product details

The Infineon CY7C1308DV25C-167BZCT is officially marked Obsolete. This means the manufacturer has discontinued production and no longer supports new orders through the standard supply chain. A board-level redesign may be required for a functional substitute.

9 Mbit DDR SRAM at 167 MHz

This is a 9 Mbit synchronous DDR SRAM organized as 256K x 36. The 167 MHz clock frequency delivers double-data-rate transfers on each clock edge, effectively doubling the read/write bandwidth compared to a single-data-rate part at the same clock. The 36-bit wide data bus suits high-throughput applications like network buffers, cache controllers, and DSP memory. Operating from a 2.4 V to 2.6 V supply, it runs at a lower core voltage than legacy 3.3 V SRAM, reducing dynamic power.

165-ball FBGA package — board integration

Housed in a 165-ball LBGA with a supplier device package of 165-FBGA measuring 13x15 mm. This fine-pitch BGA requires a multi-layer PCB with controlled impedance traces for the 167 MHz DDR interface. The tape-and-reel packaging is suited for automated pick-and-place assembly.

Frequently asked questions

What is the memory organization and clock speed of CY7C1308DV25C-167BZCT?

It is a 9 Mbit DDR SRAM organized as 256K x 36 with a 167 MHz clock. The double-data-rate interface transfers data on both clock edges, giving an effective data rate of 334 MT/s on the 36-bit bus.