36 Mbit QDR II+ buffer memory — obsolete, sourced per RFQ
The CY7C1264XV18-366BZXC: The 366 MHz clock rate delivers a peak bandwidth of 14.6 Gbps across the 36-bit parallel interface — sized for high-throughput packet buffers, traffic managers, and network processor lookaside memories where read and write buses run independently. Infineon lists this part as Obsolete.
Supply rails and temperature grade
Runs from a 1.7 V to 1.9 V core supply — a tight 200 mV window that demands a clean, low-noise rail.
165-ball FBGA footprint
Housed in a 165-ball LBGA (13x15 mm body, 1.0 mm ball pitch). The 165-FBGA (13x15) supplier package variant uses the same footprint but with a different ball-map suffix — verify the layout against the Cypress/Infineon footprint drawing before committing the PCB.