36 Mbit DDR II+ SRAM at 400 MHz — what it buys you
The CY7C1250KV18-400BZC is a 36 Mbit synchronous SRAM from Infineon (formerly Cypress) using the DDR II+ architecture, organized as 1M x 36 and clocked at 400 MHz. The DDR II+ interface delivers back-to-back read/write transactions every clock edge — no dead cycles on the bus — which matters when the memory sits between a high-throughput ASIC or FPGA and a 36-bit data path.
400 MHz clock — bus timing headroom
At 400 MHz the clock period is 2.5 ns. The DDR II+ interface samples data on both edges, so the effective data rate is 800 MT/s per pin. For a 36-bit word that is 3.2 GB/s of raw bandwidth. The synchronous pipeline keeps output valid across the full clock cycle, which relaxes the setup/hold budget at the controller side — useful when trace lengths push beyond 50 mm on the FBGA breakout.
Package and supply — layout checklist
The 165-FBGA (13×15 mm) is a fine-pitch BGA — expect 1.0 mm ball pitch or finer.
