Infineon CY7C1165KV18-550BZC, QDR II+ synchronous SRAM, 18 Mbit, 512K x 36, 550 MHz clock, parallel interface, 1.7V–1.9V supply, 165-FBGA (13x15 mm), commercial temperature 0°C to 70°C.
| Parameter | Value |
|---|---|
| Memory type | Volatile |
| Mounting | Surface Mount |
| Supply voltage | 1.7V ~ 1.9V |
| Clock frequency | 550 MHz |
| Memory interface | Parallel |
| Operating temperature | 0°C ~ 70°C (TA) |
| Package | Tray |
| Technology | SRAM - Synchronous, QDR II+ |
| Memory size | 18Mbit |
| Memory format | SRAM |
| Case | 165-LBGA |
| Memory organization | 512K x 36 |
The CY7C1165KV18-550BZC is an 18 Mbit synchronous SRAM built on Infineon's QDR II+ architecture, clocked at 550 MHz. QDR II+ eliminates the bus-turnaround dead cycles that plague standard synchronous SRAMs, delivering sustained read-write throughput on every clock edge. For a network line card or test instrument that streams data into an FPGA at line rate, this part keeps the pipeline full without wait states. The memory is organized 512K x 36.
The CY7C1265XV18-633BZXC is a higher-density (36 Mbit) and higher-speed (633 MHz) sibling in the same QDR II+ family, but it is not a pin-compatible second source — expect a different ball map and package option (Bulk vs Tray). For a direct functional replacement at the same 18 Mbit density and 550 MHz speed, there is no exact second-source listed in the Infineon portfolio.
The part ships in a Tray and uses a 165-ball FBGA package (13x15 mm body) for surface-mount assembly.
It is a synchronous SRAM using the QDR II+ architecture, which eliminates bus-turnaround dead cycles for sustained back-to-back read/write throughput.