It clocks at 400 MHz, delivering back-to-back read and write transactions on separate buses without dead cycles — the defining advantage of QDR (Quad Data Rate) over conventional DDR or NoBL SRAMs. The memory interface is parallel, the supply range is 1.7V to 1.9V, and it comes in a 165-ball FBGA (13x15 mm) for surface-mount assembly.
This part is officially marked Obsolete by Cypress (now Infineon). If you are supporting a legacy design that already uses this exact footprint and timing, you will need to source from brokers or excess inventory holders.
400 MHz clock — bus margin and throughput
At 400 MHz, the QDR II+ interface delivers a peak bandwidth of 28.8 Gbit/s (36-bit data bus × 400 MHz × 2 for DDR on each of the read and write ports). That throughput is the reason to pick this part over a lower-frequency SRAM. The trade-off is tighter timing closure on the PCB — the 400 MHz clock demands controlled impedance, matched trace lengths, and clean supply decoupling. If your system cannot maintain signal integrity at this speed, consider a 250 MHz or 300 MHz QDR II+ variant in the same family.
The 165-ball FBGA (13x15 mm) is a fine-pitch BGA requiring a reflow profile typical for lead-free assemblies.