It clocks at 400 MHz on the read and write ports simultaneously, delivering back-to-back transactions without the dead cycles that plague standard synchronous SRAMs on bus-turnaround.
At 400 MHz each port delivers a 400 MT/s data rate. The QDR II+ architecture separates the read and write data buses, meaning the controller never stalls waiting for direction reversal.
Last-time-buy — what it means for procurement
Infineon has placed the CY7C1145KV18-400BZXC into Last Buy status. This is not an NRND or a gradual phase-out — it is the final ordering window before the part becomes unavailable from the factory. Any production run, repair stock, or buffer allocation that depends on this exact order code needs to be committed now. For BOM lines that cannot requalify, the independent channel is the only post-LTB source.
Package and layout notes for the 165-FBGA
The 165-ball FBGA measures 13 mm by 15 mm. The commercial temperature grade means the part is characterized only to 70°C ambient.