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Infineon Technologies CY7C109B-15VC — Memory (DRAM / SRAM / Flash / EEPROM)

CY7C109B-15VC SRAM 1Mbit 15ns 32-SOJ Infineon Obsolete

MPNCY7C109B-15VC
Obsolete

Infineon CY7C109B-15VC, 1Mbit asynchronous SRAM, 128K x 8 organization, 15 ns access time, 4.5V–5.5V supply, 32-SOJ surface-mount package, tube.

Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

CY7C109B-15VC specifications
ParameterValue
Memory typeVolatile
MountingSurface Mount
Supply voltage4.5V ~ 5.5V
Memory interfaceParallel
Operating temperature0°C ~ 70°C (TA)
PackageTube
TechnologySRAM - Asynchronous
Access time15 ns
Memory size1Mbit
Memory formatSRAM
Case32-BSOJ (0.400\", 10.16mm Width)
Memory organization128K x 8
Write cycle time - word, page15ns

Product details

The CY7C109B-15VC is a 1Mbit asynchronous SRAM organized as 128K x 8 bits, with a 15 ns access time and a parallel interface. It operates from a 4.5V to 5.5V supply, placing it in legacy 5V logic systems — not a 3.3V drop-in. The 32-SOJ package (0.400-inch body width) is a surface-mount footprint common in late-1990s through mid-2000s embedded and telecom boards.

Obsolete — sourcing through distribution

Infineon lists the CY7C109B-15VC as Obsolete.

Frequently asked questions

How can I order CY7C109B-15VC or check stock?

The CY7C109B-15VC is obsolete and no longer in production. We source from available inventory and quote to order against your BOM quantity. Submit an RFQ for current availability and pricing — no stock-holding claim on this page.

Is there a direct replacement for CY7C109B-15VC?

No official successor is listed by Infineon. A functionally equivalent 1Mbit asynchronous SRAM in a 32-SOJ package with 15 ns access and 5V supply would need to be verified pin-for-pin and timing-compatible. The 3.3V SRAMs common today are not drop-in replacements due to the supply voltage difference.

Can CY7C109B-15VC be replaced by a 3.3V SRAM?

No — the CY7C109B-15VC requires a 4.5V–5.5V supply. A 3.3V SRAM would need a level translator on the address/data bus and a separate 3.3V rail, which is not a pin-compatible swap.