16 Mbit asynchronous SRAM with a 10 ns window
The parallel interface and 10 ns write cycle time mean it can keep up with a fast controller or FPGA without inserting wait states, provided the address-to-data setup budget is tight.
10 ns access time — bus margin, not just a number
For a 100 MHz bus (10 ns cycle), that leaves zero margin for address decoding and board trace delay — you need a slower clock or a pipelined controller. At 66 MHz (15 ns cycle), the 10 ns access gives a 5 ns window for the glue logic and PCB flight time, which is workable with careful layout.
The 2.2 V minimum supply also helps in battery-backed or low-voltage-drop designs where the rail sags under load.