10 ns asynchronous SRAM for 5V bus-timing-critical designs
The CY7C1061GE-10ZXIT: This part is built for legacy 5V logic systems where the bus timing margin depends on single-cycle random access — think motor drive control boards, telecom line cards, and industrial PLCs that still run a 5V backplane.
10 ns access — what it buys on the bus
4.5V–5.5V supply — not a 3.3V part
The supply range is 4.5V to 5.5V, which is a straight 5V ±10% rail. This part is not compatible with 3.3V-only systems — the inputs and core logic expect 5V levels. If your board has a 3.3V bus, you need a level translator or a different SRAM. For a 5V legacy design, the 4.5V minimum gives headroom through a 5V rail that sags under load; the 5.5V max covers a regulated 5V supply with a few percent tolerance.
54-TSOP II — footprint and rework
The package is a 54-TSOP II (0.400" body width, 10.16 mm).
