16-Mbit asynchronous SRAM in a 48-TSOP I footprint
The Infineon CY7C1061G30-10ZXET is a 16 Mbit asynchronous SRAM organized 1M x 16, with a 10 ns access time that sets the bus cycle ceiling for the memory controller. Housed in a 48-TSOP I (0.724" body width), this surface-mount package routes 48 pins on a 0.50 mm pitch — the same footprint as the industry-standard TSOP I pinout, so it drops onto existing board layouts without a spin.
