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Infineon Technologies CY7C1061G-10ZXI — Memory (DRAM / SRAM / Flash / EEPROM)

Cypress CY7C1061G-10ZXI 16Mbit Async SRAM, 10 ns, 48-TSOP I

MPNCY7C1061G-10ZXI
Active

Cypress CY7C1061G-10ZXI, 16Mbit asynchronous SRAM, 1M x 16 parallel organization, 10 ns access time, 4.5–5.5V supply, 48-TFSOP (48-TSOP I) package, -40°C to 85°C operating temperature, Tray.

$38.5000Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

CY7C1061G-10ZXI specifications
ParameterValue
Memory typeVolatile
MountingSurface Mount
Supply voltage4.5V ~ 5.5V
Memory interfaceParallel
Operating temperature-40°C~85°C(TA)
PackageTray
TechnologySRAM - Asynchronous
Access time10 ns
Memory size16Mbit
Memory formatSRAM
Case48-TFSOP (0.724\", 18.40mm Width)
Memory organization1M x 16
Write cycle time - word, page10ns

Product details

That access-time figure is the one that decides whether your memory controller can do back-to-back reads at full clock rate or needs to stall. It comes in a 48-TFSOP (18.40 mm width) package, also known as 48-TSOP I, a standard footprint for this density class.

Industrial temperature range — where it lives

The 10 ns write-cycle time (word and page) matches the read access, so the bus timing budget is symmetric — no penalty for mixing read and write transactions.

Package and rework

The Tray shipping medium means the parts arrive aligned in a carrier, not loose in a bag; for hand-assembly or small-batch rework, that saves a sorting step.

Listed as Active — no last-time-buy risk, no imminent obsolescence.

Frequently asked questions

What is the access time of CY7C1061G-10ZXI?

The access time is 10 ns for both read and write cycles (word and page). That is fast enough to feed a 100 MHz bus without wait states.

Does CY7C1061G-10ZXI fit a standard 48-TSOP I footprint?

Yes. The package is a 48-TFSOP (0.724", 18.40 mm width), also referred to as 48-TSOP I. It is a standard surface-mount footprint for 16Mbit asynchronous SRAMs and is pin-compatible with many other 48-TSOP I parts of the same density and organization.

What is the difference between CY7C1061G-10ZXI and CY7C1061G-10ZXC?

All other specifications — 16Mbit density, 1M x 16 organization, 10 ns access time, 4.5–5.5V supply, 48-TSOP I package — are identical.