16 Mbit asynchronous SRAM in a 54-TSOP II footprint
The CY7C1061G-10ZSXIT: The 54-TSOP II package (0.400-inch body width) is a standard footprint for high-density SRAM in telecom and industrial controllers — the 10 ns access time gives the bus a comfortable timing margin for 66 MHz-class microcontrollers without wait states.
Last Buy — plan your final order window
If this SRAM is on your BOM, now is the time to commit to a lifetime buy quantity — once the Last Buy closes, the only source will be the open market.
5 V supply and industrial temperature range
The 10 ns write cycle time (word and page) matches the read access — no penalty for mixed read/write traffic in a cache or buffer application.
