16 Mbit asynchronous SRAM for 5 V bus systems
The parallel interface and asynchronous architecture simplify board layout by eliminating the need for a clock signal.
10 ns access time — timing margin for high-speed buses
In a 5 V system running a 50 MHz bus (20 ns cycle), a 10 ns SRAM leaves a 10 ns window for address decode, setup, and hold — enough margin to avoid wait states with most CPLD-based glue logic.
Package and footprint: 48-VFBGA (6x8 mm)
No official second source is recorded, but the CY7C1061 family is widely used, so cross-sourcing through independent distribution is straightforward.
