10 ns asynchronous SRAM in a 48-ball VFBGA
16 Mbit in a 1M x 16 word width
The 1M x 16 organization maps directly to a 16-bit data bus without needing byte-lane muxing — a clean fit for systems that want a single-chip data memory with no glue logic. The 10 ns access time and 10 ns write cycle mean the SRAM can keep up with zero-wait-state back-to-back accesses from a 100 MHz-class bus master, assuming the board layout keeps trace lengths reasonable.
It needs a solder-paste stencil designed for the 6x8 array and a reflow profile that matches the JEDEC moisture sensitivity level (MSL) on the bag label. Tape & Reel supply means it feeds straight into a pick-and-place; no tube or tray handling.
Active lifecycle — no near-term LTB
Listed as active in production. If you need a production commitment, this is the version to qualify.
