4Mbit asynchronous SRAM with 10 ns access
The CY7C1041GN30-10VXI is a 4Mbit asynchronous SRAM organised as 256K x 16 bits, with a 10 ns access time that sets the read-cycle timing floor for the bus interface. The 10 ns spec means the part can keep up with a 100 MHz bus clock without wait states, assuming the controller's address-to-data setup is within that window.
The supply range of 2.2V to 3.6V covers both 2.5V and 3.3V nominal rails, so a single BOM line can serve mixed-voltage systems without a translator.
Active lifecycle and package reality
Infineon lists the CY7C1041GN30-10VXI as Active. The part ships in a 44-SOJ surface-mount package, a JEDEC-standard body that mates with SOJ sockets or direct-solder pads. The Tube delivery quantity is the factory-standard pack; reels are not listed for this order code.