10 ns asynchronous SRAM for cacheless bus timing
The 10 ns access means a 100 MHz bus master can complete a read in one cycle without inserting wait states, assuming the address-to-data path stays within budget. The 16-bit wide word matches the data bus of a 16-bit MCU or DSP directly, eliminating the need for byte-lane steering logic.
The 44-SOJ package (44-BSOJ, 0.400" body width, 10.16 mm wide) is a surface-mount footprint with J-bend leads — common on memory modules and legacy industrial designs. The J-bend gives a smaller footprint than an SOIC but still allows visual solder-joint inspection.
The base product number CY7C1041 covers multiple speed and temperature variants, so if the 10 ns grade or industrial temp is not critical, a sibling in the same package may also be available.