10 ns access time — bus margin for the processor
Infineon lists the CY7C1041G30-10BVJXIT as Active. No last-time-buy window, no end-of-life risk for the BOM.
Voltage and organization — drop-in fit for 3.3V buses
Runs from 2.2V to 3.6V, so it mates directly with a 3.3V FPGA or processor bank without a level shifter. Organized 256K x 16 — 16-bit data bus, 18 address lines. The parallel interface is asynchronous: no clock, no strobe sequencing. The write cycle time matches the read access at 10 ns, so page-mode or word writes run at the same speed.