4Mbit async SRAM with 10 ns access — the timing-critical cache line
The Infineon CY7C1041D-10ZSXI is a 4Mbit asynchronous SRAM organized as 256K x 16 bits, delivering a 10 ns access time that suits high-speed cache, FIFO buffers, and real-time control memory in networking gear and industrial controllers. Packaged in a 44-TSOP II (0.400" body width, 10.16 mm), it is a surface-mount footprint common to mid-density asynchronous SRAMs, making it a drop-in for many existing board layouts.
In a system with a 40 MHz bus, that 10 ns window gives the designer headroom to add glue logic or a CPLD between the controller and the SRAM without violating timing closure.
No official successor part is listed by Infineon for this specific variant.
Package note for the rework bench
The 44-TSOP II is a thin small-outline package with 0.8 mm pitch gull-wing leads. The 10.16 mm body width means it sits on a standard 0.65 mm pitch socket for programming or test.