12 ns asynchronous SRAM for the timing-critical bus
The Infineon CY7C1041CV33-12ZSXET is a 4Mbit asynchronous SRAM organized as 256K x 16, with a 12 ns access time.
This part comes in a 44-TSOP II package (0.400" body width, 10.16 mm). The surface-mount TSOP II footprint is shared across 4Mbit and 8Mbit parts from multiple vendors.
That removes the sourcing risk for new designs and production runs — you're not chasing broker stock or managing a phase-out window. For a 4Mbit asynchronous SRAM in a standard TSOP II package, this is about as stable a supply position as you'll find.