20 ns asynchronous SRAM for legacy 5 V buses
The Infineon CY7C1041BN-20ZSXAT is a 4Mbit asynchronous SRAM organized as 256K x 16, with a 20 ns access time. The 44-TSOP II footprint is common across the CY7C1041 family, so board layout carries over if you swap density variants.
What the 20 ns access time buys the bus
The 20 ns access time means the SRAM can deliver data within 20 ns of the address being valid, which is fast enough to work with 5 V CPLDs, legacy ASICs, and older microcontrollers that run bus cycles in the 40–50 ns range. If your controller's read strobe is tighter than 25 ns, you will need to check setup-and-hold margins against the datasheet's AC timing table — the 20 ns figure is the ceiling, not the typical.