15 ns access time — what it means for the bus
The 15 ns access time sets the window from address valid to data valid on a read cycle. The write cycle time matches at 15 ns.

Infineon CY7C1041B-15ZC, 4Mbit asynchronous SRAM, 256K x 16 organization, 15 ns access time, 4.5V–5.5V supply, 44-TSOP II, commercial temperature 0°C to 70°C, tray.
| Parameter | Value |
|---|---|
| Memory type | Volatile |
| Mounting | Surface Mount |
| Supply voltage | 4.5V ~ 5.5V |
| Memory interface | Parallel |
| Operating temperature | 0°C~70°C(TA) |
| Package | Tray |
| Technology | SRAM - Asynchronous |
| Access time | 15 ns |
| Memory size | 4Mbit |
| Memory format | SRAM |
| Case | 44-TSOP (0.400\", 10.16mm Width) |
| Memory organization | 256K x 16 |
| Write cycle time - word, page | 15ns |
The 15 ns access time sets the window from address valid to data valid on a read cycle. The write cycle time matches at 15 ns.
The access time is 15 ns, which also matches the write cycle time for word and page operations.
Yes, the CY7C1041B-15ZC is designed for a 4.5V to 5.5V supply, making it a native 5V part suitable for legacy 5V bus systems.