10 ns asynchronous SRAM — 256K x 24 organization
This is a 6 Mbit asynchronous SRAM organized as 256K words by 24 bits — an uncommon width that suits 24-bit DSP datapaths, graphics pixel pipelines, or wide glue-logic buffers. The 10 ns access time and 10 ns write cycle (word, page) mean it can keep up with a 100 MHz bus without wait states, provided the board trace delay and capacitive loading are within budget. Supply range is 3.0 V to 3.6 V, typical for 3.3 V logic families. The parallel interface is straightforward to route — no clock, no DLL, no refresh overhead. The 119-PBGA (14x22 mm) footprint requires a 4-layer PCB minimum for fan-out; the 0.50 mm ball pitch calls for via-in-pad or microvia if the inner rows are used.
Industrial temperature grade — field deployment fit
The 119-PBGA package's thermal coefficient matches standard FR-4; no special underfill is required for the industrial range, but the moisture sensitivity level (MSL) should be confirmed before reflow.