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Infineon Technologies CY7C1021D-10ZSXAT — Memory (DRAM / SRAM / Flash / EEPROM)

CY7C1021D-10ZSXAT Infineon 1Mbit Async SRAM 10 ns 44-TSOP II

MPNCY7C1021D-10ZSXAT
Obsolete

Infineon Technologies CY7C1021D-10ZSXAT, 1Mbit (64K x 16) asynchronous SRAM, 10 ns access time, 4.5V–5.5V supply, -40°C to 85°C, 44-TSOP II, Tape & Reel

$4.4800Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

CY7C1021D-10ZSXAT specifications
ParameterValue
Memory typeVolatile
MountingSurface Mount
Supply voltage4.5V ~ 5.5V
Memory interfaceParallel
Operating temperature-40°C ~ 85°C (TA)
PackageTape & Reel (TR)
TechnologySRAM - Asynchronous
Access time10 ns
Memory size1Mbit
Memory formatSRAM
Case44-TSOP (0.400\", 10.16mm Width)
Memory organization64K x 16
Write cycle time - word, page10ns

Product details

5V asynchronous SRAM for legacy bus hold

The CY7C1021D-10ZSXAT is a 1Mbit asynchronous SRAM organized as 64K x 16, with a 10 ns access time that keeps the bus timing margin comfortable for 5V legacy controllers running at 50–66 MHz.

Infineon lists the CY7C1021D-10ZSXAT as Obsolete. We source this part through our independent supply network against your BOM quantity.

44-TSOP II footprint and supply rails

The 44-TSOP II package (0.400-inch body width, 10.16 mm) is a standard SRAM footprint used across Cypress/Infineon and ISSI families — verify the pin 1 orientation against your existing layout before committing. The 4.5V–5.5V supply range is compatible with legacy 5V TTL buses; no level translation is needed when interfacing to 5V-tolerant CPLDs or ASICs.

Frequently asked questions

How can I order CY7C1021D-10ZSXAT or check availability?

Submit an RFQ with your target quantity and lead-time window. We source this obsolete SRAM through our independent supply chain and confirm price and delivery at quote time.

Is CY7C1021D-10ZSXAT compatible with 5V logic?

Yes, the supply range is 4.5V to 5.5V, which directly matches 5V TTL buses. No level translation is required when connecting to 5V-tolerant controllers or FPGAs.