1 Mbit async SRAM — 12 ns access, 64K x 16 organization
The Infineon CY7C1021CV33-12VXC is a 1 Mbit asynchronous SRAM organized as 64K words by 16 bits. The parallel interface uses a 16-bit data bus and separate address lines, with chip enable and output enable controls for simple bus sharing.
44-SOJ footprint — surface-mount, 10.16 mm body width
The J-lead form factor saves board area versus a DIP while keeping a visible solder joint for inspection. The 44-SOJ footprint is common across Cypress/Infineon 1 Mbit async SRAMs of this generation, so a layout designed for the CY7C1021 family accepts this part without a board spin.
Infineon lists the CY7C1021CV33-12VXC as obsolete.