1 Mbit asynchronous SRAM for 5 V legacy buses
The parallel interface eliminates the need for a memory controller, simplifying the glue logic on a legacy 5 V backplane.
15 ns access time — timing margin for fast processors
The 64K x 16 organization maps directly to a 16-bit data bus, saving the byte-lane muxing that an 8-bit-wide memory would require.
No last-time-buy window is available from the manufacturer.
