Infineon lists the CY7C1020DV33-10VXIT as Obsolete.
10 ns access, 32K x 16 organization
This is a 512Kbit asynchronous SRAM organized as 32K words by 16 bits. The 10 ns access time and 10 ns write cycle time mean the memory can keep up with fast bus transactions without wait states — a tight fit for cache or scratchpad in embedded systems where the CPU clock is below 100 MHz.
44-SOJ package, parallel interface
Housed in a 44-SOJ (Small Outline J-lead) package, the CY7C1020DV33-10VXIT uses a parallel memory interface — address and data lines are direct, no serial protocol overhead. The surface-mount package is suited for reflow assembly; the J-lead footprint is standard for SOJ-44.