12 ns access — timing margin for a 5 V bus
The CY7C1020B-12ZXC: 512Kbit asynchronous SRAM organized as 32K x 16 bits, with a 12 ns access time.
Obsolete — no official replacement listed
44-TSOP II — footprint for legacy memory slots
Housed in a 44-TSOP (0.400", 10.16 mm width) surface-mount package, this SRAM uses the industry-standard JEDEC pinout for 32K x 16 asynchronous SRAMs.
