10 ns async SRAM for legacy 5V buses
This part is typically used in legacy networking gear, industrial controllers, and test equipment that still run on a 5V memory bus and need fast, no-wait-state random access.
In a 5V system with a 50 MHz bus (20 ns cycle), this leaves 10 ns of setup margin before the controller latches data — tight but workable with controlled PCB trace lengths.
Package and footprint: 32-SOIC wide body
The part comes in a 32-SOIC package with 0.400-inch body width (10.16 mm), surface-mount.
