576Kbit synchronous dual-port SRAM — 6.5 ns access time, 100 MHz clock
The Infineon CY7C09189V-6AXC is a 576Kbit synchronous dual-port SRAM organized as 64K x 9 bits, with a 6.5 ns access time and a 100 MHz clock. The x9 organization provides eight data bits plus a parity bit per word, useful for error-detection schemes in shared-memory designs. The 6.5 ns access time at 100 MHz clock means the part can sustain back-to-back read/write cycles with minimal dead cycles on the bus. For a dual-port SRAM used as a mailbox or FIFO buffer between two clock domains, this timing margin is the critical parameter — it determines whether the bus interface can close timing without wait states.