15 ns dual-port SRAM for shared-memory designs
The Cypress CY7C057V-15AC is a 1.152Mbit dual-port asynchronous SRAM organized as 32K words by 36 bits.
32K x 36 — the 36-bit word width matters
The 32K x 36 organization means each word is 36 bits wide — 32 data bits plus 4 bits that can carry parity or ECC. This is a deliberate choice for systems that need error detection on the shared bus without adding external logic. If your design uses a narrower bus (16-bit or 32-bit without parity), the extra bits are simply unused, but the pin count and footprint are fixed at 144 pins.
If your BOM line is locked to this exact order code, plan for a one-time buy or identify a pin-compatible alternative before stock tightens further.
