15 ns dual-port SRAM — shared-memory mailbox for multiprocessor buses
The Cypress CY7C056V-15AXC is a 576Kbit dual-port asynchronous SRAM organized as 16K x 36 bits. Its 15 ns access time allows two independent processors or controllers to read and write the same memory array with minimal wait-state insertion on a shared bus — the dual-port architecture eliminates the arbitration logic a single-port RAM would need for a mailbox or FIFO buffer between two clock domains.
