The CY7C028AV-25AXCT is a 1Mbit dual-port asynchronous SRAM organized as 64K x 16 bits, with a 25 ns access time and a parallel interface. It allows two independent bus masters to read and write the same memory array without external arbitration logic.
25 ns access — what it means for bus timing
In a dual-port system, both ports can initiate a cycle simultaneously; the internal arbitration logic resolves collisions with a fixed priority scheme.
