Infineon CY7C025-55AXC, SRAM - Dual Port, Asynchronous, 128Kbit (8K x 16), 55 ns access time, 4.5V~5.5V supply, 100-TQFP, 0°C~70°C.
| Parameter | Value |
|---|---|
| Memory type | Volatile |
| Mounting | Surface Mount |
| Supply voltage | 4.5V ~ 5.5V |
| Memory interface | Parallel |
| Operating temperature | 0°C~70°C(TA) |
| Package | Tray |
| Technology | SRAM - Dual Port, Asynchronous |
| Access time | 55 ns |
| Memory size | 128Kbit |
| Memory format | SRAM |
| Case | 100-LQFP |
| Memory organization | 8K x 16 |
| Write cycle time - word, page | 55ns |
The Infineon CY7C025-55AXC is a 128Kbit dual-port asynchronous SRAM organized as 8K x 16. Two independent ports allow simultaneous read/write access from separate bus masters.
The 55 ns access time governs how fast the memory can present data after the address is stable. In a dual-port part, that number also sets the minimum arbitration window.
The CY7C025-55AXC is officially obsolete per Infineon's lifecycle status. No last-time-buy window remains open; the part is no longer manufactured.
Yes, the CY7C025-55AXC is obsolete per Infineon's lifecycle status. It is no longer in production and has no active last-time-buy window. Sourcing is limited to surplus or broker inventory.
There is no pin-compatible direct replacement from Infineon in the same 5 V, 100-TQFP package. A redesign would be required to use a different dual-port SRAM family or a single-port SRAM with external arbitration.
We source the CY7C025-55AXC to order against an RFQ through our independent distribution network. Availability and current pricing are confirmed at quote time — submit an RFQ for a firm quote.
The access time is 55 ns, which sets the bus timing window for read operations and arbitration in a dual-port configuration.
It comes in a 100-TQFP (14x14 mm) surface-mount package with 0.5 mm pitch.