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Infineon Technologies CY62148DV30LL-55ZSXI — Microcontrollers & Processors (MCU / MPU / DSP)
Infineon Technologies

Infineon CY62148DV30LL-55ZSXI SRAM, 4Mbit, 55ns, 32-SOIC

MPNCY62148DV30LL-55ZSXI
End of Life

Infineon Technologies MoBL® series, SRAM - Asynchronous, 4Mbit, 512K x 8, Parallel interface, 55 ns access, 2.2V ~ 3.6V, -40°C ~ 85°C, 32-SOIC (0.445", 11.30mm Width), Surface Mount, Bulk.

$2.37Ref. price · indicative, final on quote
CY62148DV30LL-55ZSXI datasheet
Packaging32-SOIC (0.445", 11.30mm Width)
StockIn Stock (28)
Lead timeIn Stock wk
MOQ1 pcs
  • 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
  • Date & lot codes on quoteStated per line before you commit; label photos on request.
  • MSL-compliant ESD packingMoisture-sealed bags with indicator cards; reels photo-verified.
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Specifications

CY62148DV30LL-55ZSXI Technical Specifications
ParameterValue
SeriesMoBL®
Memory typeVolatile
Mounting typeSurface Mount
Voltage2.2V ~ 3.6V
Memory interfaceParallel
Operating temperature-40°C ~ 85°C (TA)
PackageBulk
TechnologySRAM - Asynchronous
Access time55 ns
Memory size4Mbit
Memory formatSRAM
Case32-SOIC (0.445\", 11.30mm Width)
Memory organization512K x 8
Write cycle time - word, page55ns

Product details

4 Mbit asynchronous SRAM in a 32-pin SOIC

The Infineon CY62148DV30LL-55ZSXI is a 4 Mbit asynchronous SRAM organized as 512K x 8 bits, with a 55 ns access time. It sits in the MoBL® series, a low-power family designed for battery-backed and portable applications where standby current matters.

55 ns access and 512K x 8 organization

The 55 ns access time means the part can deliver data within 55 ns of a valid address — fast enough for most 8-bit and 16-bit microcontroller buses running at moderate clock rates, but not intended for high-speed cache or DSP scratchpad duty. The 512K x 8 organization (byte-wide) is a natural fit for 8-bit data buses and simplifies PCB routing compared to a x16 part when only byte-wide access is needed. The write cycle time matches the read access at 55 ns, so no wait-state penalty on back-to-back writes.

Active production, RoHS3 compliant

It is fully RoHS3 compliant (2011/65/EU + 2015/863).

Frequently asked questions

What is the memory organization and access time of CY62148DV30LL-55ZSXI?

It is organized as 512K x 8 bits (4 Mbit total) with a 55 ns access time and a matching 55 ns write cycle time.

What compliance documentation does Infineon provide for CY62148DV30LL-55ZSXI?

The part is RoHS3 compliant (ROHS3). Infineon provides a RoHS certificate and material declaration upon request through the RFQ process.