1 Mbit asynchronous SRAM with 55 ns access
The CY62128ELL-55SXET is a 1 Mbit asynchronous SRAM from the MoBL® series, organized as 128K x 8 bits. The 55 ns access time sets the fastest read or write cycle the bus can sustain — a 5V logic system running at 18 MHz or slower can hit this without wait states. Supply range is 4.5V to 5.5V, so it drops straight into legacy 5V parallel buses without a level translator.
Housed in a 32-SOIC wide-body (0.445" body width, 11.30 mm), the footprint is hand-solderable with a fine-tip iron — no hot-air or reflow oven required for prototyping.
