55 ns access, 1 Mbit parallel SRAM
The CY62128BLL-55ZAC is a 1 Mbit asynchronous SRAM from Cypress's MoBL® series, organized as 128K x 8 bits with a 55 ns access time.
Read and write timing
The 55 ns access time and 55 ns write cycle time set the bus timing floor — the processor must hold address and control signals stable for at least that window. The parallel interface means all eight data bits are available on the same cycle, so the memory controller's setup-and-hold budget is the same for both read and write operations.
Temperature grade and package
The 32-TSOP is a standard thin small-outline package with a 0.50 mm pitch — the footprint matches JEDEC MO-142, so a single PCB layout serves multiple SRAM suppliers.
Listed as active in production. The part is RoHS non-compliant — the lead finish is likely tin-lead, which matters for EU RoHS-exempt applications (military, aerospace, medical implant) or for legacy BOMs that require the original solder profile.