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Infineon Technologies 5962-8858702XA — Memory (DRAM / SRAM / Flash / EEPROM)
Infineon Technologies

5962-8858702XA 4Kbit Parallel SRAM, 35 ns, Ceramic Flatpack

MPN5962-8858702XA
End of Life

5962-8858702XA — 4Kbit parallel SRAM, 4K x 1 organization, 35 ns access time, 4.5 V supply, 18-pin ceramic flatpack, -55°C to 125°C operating temperature, surface-mount.

$104.66Ref. price · indicative, final on quote
5962-8858702XA datasheet
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Specifications

5962-8858702XA Technical Specifications
ParameterValue
Interface_typeParallel
Mounting_typeSurface Mount
Operating temperature high-55°C to 125°C(TA)
Frame_size4Kbit
Access time35 ns
Memory_typeVolatile
Package_typeBulk
Memory formatSRAM
Supply_voltage_v4.5
Memory organization4K x 1
Write cycle time - word, page35ns

Product details

4Kbit parallel SRAM in a ceramic flatpack — what this part is and where it fits

The 5962-8858702XA is a 4Kbit parallel SRAM organized as 4K x 1 bit, with a 35 ns access time and a 4.5 V supply rail. It is packaged in an 18-pin ceramic flatpack (CFLATPACK) and rated for the full military temperature range of -55°C to 125°C. This is a volatile memory — data is lost when power drops — intended for high-reliability applications where a small, fast scratchpad or status register is needed: avionics memory-mapped I/O, satellite telemetry buffers, or missile-guidance sequencer storage. The 4K x 1 organization means each address returns a single bit, so this part is typically used in parallel banks for wider data words or as a single-bit-wide holding register, not for code execution or multi-byte data arrays.

35 ns access time — bus timing constraint

Access time is 35 ns; write cycle time is 35 ns.

Frequently asked questions

Will 5962-8858702XA drop into a board designed for 5962-8961415QXA?

No. The 5962-8961415QXA is a 1Mbit EPROM in a through-hole package with 45 ns access time, while the 5962-8858702XA is a 4Kbit SRAM in a surface-mount ceramic flatpack. They are not pin-compatible or functionally interchangeable without a board redesign.

What is the memory organization and interface of 5962-8858702XA?

It is organized as 4K x 1 bit (one bit per address) with a parallel interface. The 35 ns access time and 35 ns write cycle time are symmetric.