Frequency accuracy and tolerance
The ECS-120-18-5PVX: The 18pF load capacitance is the circuit-design target — the Pierce oscillator on the MCU or SoC needs matching capacitors on each side of the crystal totalling 18 pF in parallel, so 33 pF on each pin is the standard starting point before trimming for exact frequency. ±50 ppm frequency stability covers the drift across the full -10°C to +70°C operating window; the ±30 ppm tolerance is what you measure at 25 °C before any temperature is applied. Together they define the clock accuracy budget — for a UART at 12 MHz, ±50 ppm over temperature keeps the baud-rate error well within the ±2 % tolerance most UARTs tolerate. 60 Ω ESR maximum means the crystal starts reliably in a properly biased Pierce circuit; the ESR specification matters more for low-power designs where the drive level is marginal, not for a standard MCU clock.
HC-49/US package and SMT handling
HC-49/US is the traditional half-can outline scaled for surface-mount reflow — the housing is smaller than the full-depth HC-49 variants you'll still find on some through-hole BOMs, so confirm the land-pattern dimensions match your pad geometry before the layout ships. Tape-and-reel packaging suits standard pick-and-place; the 11.40 mm x 4.80 mm body fits the standard pocket, and the 2.60 mm seated height is within the clearance budget for most single-sided or low-profile SMT assemblies. The operating temperature grade of -10°C to 70°C is commercial, not industrial — do not specify this part for an outdoor enclosure or a panel that sees sub-zero ambient without checking whether the crystal stability derates at temperature extremes beyond the listed window.
Sourcing the CSM-7SSX 12 MHz
Quoted to order against your BOM quantity through independent distribution channels. Lead time and availability confirmed at RFQ — the reel format suits standard production runs; volume or spot-demand quantity changes are resolved at quote time rather than by an on-screen stock count.