16-bit R-2R DAC with 1µs settling
The MAX5541ESA+T is a 16-bit, voltage-unbuffered DAC built on an R-2R ladder architecture — the same topology that gives you monotonicity down to 1 LSB without the glitch energy of a segmented design. The 1 µs typical settling time to ±0.5 LSB means this part can update at roughly 1 MSPS in a single-channel system, assuming the SPI clock and output amplifier (if needed) keep pace. The unbuffered output (Voltage - Unbuffered) is a design-in detail: the R-2R network has a nominal output impedance of about 10 kΩ, so the load you drive must be high-impedance or buffered externally. If your BOM already has an op-amp on the output, this saves the cost of an internal buffer; if not, budget a rail-to-rail follower.
Single 5V supply, SPI control, SOIC-8 footprint
Both analog and digital supplies are 5 V nominal — a single 5 V rail powers the DAC core and the SPI interface logic. The SPI data interface uses standard 4-wire mode (SCLK, DIN, CS, and DOUT for daisy-chaining), and the reference is external, so the full-scale output voltage is set by the reference voltage you supply, not by the DAC's internal bandgap. Housed in an 8-pin SOIC (0.154" width, 3.90 mm body) with surface-mount termination, the board footprint is standard.
Active production, ROHS3, tape-and-reel options
ROHS3 compliant means no restricted substances in the package or plating, which clears EU and most global regulatory gates without an exemption certificate. Available in Tape & Reel (TR) or Cut Tape (CT) — the TR variant is the standard reel quantity for automated pick-and-place; CT is for prototyping or small-batch builds. The package is 8-SOIC, supplier device package 8-SOIC, so the reel tape width and pocket pitch are the SOIC-8 standard.