8-bit SAR ADC in SOT-23-8 — what the 100k SPS means for your signal chain
The MAX1115EKA+T is an 8-bit successive-approximation-register (SAR) ADC from Analog Devices, sampling at 100k samples per second over an SPI interface. The SAR architecture delivers a deterministic conversion time — no pipeline delay — so each sample is ready on the next clock edge, which matters for multiplexed or time-critical measurements where sample-to-sample jitter must stay under one conversion cycle. The single-ended input with an internal reference (MUX-S/H-ADC configuration) means the BOM keeps the reference and the input buffer off the board — the ADC handles the voltage reference internally, so the layout only needs a clean analog supply and a decoupling cap at the VREF pin.