16-bit R-2R DAC with 1 µs settling — the SPI update-rate ceiling
The LTC1595AIS8#PBF is a 16-bit, single-channel, current-output DAC built on a classic R-2R ladder architecture. Its 1 µs typical settling time to ±0.5 LSB sets the maximum update rate the SPI bus can sustain — at 20 MHz SCLK, a 16-bit frame takes 800 ns, so the DAC's own settling, not the bus, is the throughput bottleneck. Integral nonlinearity is ±0.35 LSB typical, differential nonlinearity ±0.2 LSB typical — this is a 16-bit-accurate part, not a 14-bit part trimmed to 16-bit specs. The monotonicity guarantee over temperature means the transfer curve never reverses slope, which matters for closed-loop servo and trim-DAC applications where a non-monotonic step would cause oscillation.
Single 5 V supply, external reference — simple isolation boundary
Both analog and digital supply rails are 5 V nominal — a single 5 V rail powers the DAC core and the SPI interface, which simplifies the power tree and lets a single digital isolator channel (e.g., an ADuM1401) bridge the controller-side 3.3 V domain to the DAC-side 5 V domain without a level translator. The reference input is external — the output full-scale range equals the reference voltage times the R-2R ratio. A precision reference like the LT1236 or ADR4550 sets the absolute accuracy; the DAC's own INL contribution adds on top of the reference drift. The output is current-unbuffered — the R-2R network drives the output pin directly. An external op-amp (e.g., LT1468) converts the current to a voltage; the op-amp's input bias current and offset voltage add to the DAC's own error budget. The 8-SOIC package leaves room for a dual op-amp and feedback resistors on a two-layer board.
Industrial temperature grade, active lifecycle
The part is ROHS3 compliant (no exemptions expiring), and the standard 8-SOIC footprint means no board-spin risk for a package change.