7.5 GHz SiGe clock distribution buffer
The ADCLK925BCPZ-WP is a SiGe clock buffer and data driver with a 7.5 GHz maximum frequency. It accepts a differential clock input and fans it out to two differential outputs configurable for ECL, NECL, or PECL logic levels.
Supply voltage and logic-level flexibility
The supply range spans 2.375 V to 3.63 V, covering both 2.5 V and 3.3 V rails commonly found in high-speed mixed-signal boards. That range directly determines the output swing and logic family: at 3.3 V the outputs swing PECL levels; at 2.5 V they swing NECL levels. No external level translator is needed if your downstream ADC or FPGA accepts CML or has AC-coupled ECL inputs — just match the supply to the load's common-mode requirement. The wide tolerance also helps when the 3.3 V rail droops under load; the buffer keeps running through a 300 mV dip.
The 16-lead LFCSP package (3x3 mm) with exposed pad pulls heat into the PCB ground plane; without a proper via array under the pad, junction temperature will climb faster than the ambient spec suggests.