16.384 MHz XO: what the stability spec means for your timing budget
The ASV-16.384MHZ-EC-T: 16.384 MHz is a power-of-two multiple of 1 Hz (2^14), making it a natural fit for real-time clock calibration, telecommunications timing, and any application where the PLL divides cleanly to exact baud rates.
HCMOS output and power architecture
The HCMOS output stage swings rail-to-rail at 3.3V, driving standard logic input thresholds directly — no level-translation required when the downstream device runs on the same rail. Drawing 15 mA max in normal operation, the oscillator drops to 10 µA when the enable/disable pin is pulled to the off state — a microcontroller GPIO can gate the supply rail to kill the clock during deep-sleep states, keeping the standby current budget clean.
Package footprint and thermal profile
Commercial temperature grade (-20°C to +70°C) covers indoor equipment and benign industrial environments but is not suitable for unheated outdoor enclosures or engine-adjacent locations; the stability spec does not include aging margin, so a system with a multi-year calibration interval should budget additional drift headroom.
Active status and sourcing posture
The part remains in normal production through authorized distribution channels.