TLP2766A(TP4,E

Toshiba Semiconductor

Toshiba TLP2766A(TP4,E high-speed logic output photocoupler, 20MBd data rate, 5000Vrms isolation, push-pull/totem-pole output, 6-SOIC wide-body surface-mount package, -40°C to 125°C operating range.

Toshiba Semiconductor TLP2766A(TP4,E
[IN STOCK] In Stock: 40 pcs
$2.24/ pc

Volume pricing

Buy Now

MOQ 1 · Tape & Reel (TR); Cut Tape (CT) · RoHS · EIA-481 · DAP/DDP · T/T

Technical specifications

TLP2766A(TP4,E specifications
Parameter / AttributeSpecification / Value
Input typeDC
Output typePush-Pull, Totem Pole
MountingSurface Mount
Supply voltage2.7V ~ 5.5V
Voltage - isolation5000Vrms
Voltage - forward (Vf)1.8V (Max)
Current - output (Channel)10 mA
Current - DC forward (If)25mA
Operating temperature-40°C ~ 125°C
PackageTape & Reel (TR); Cut Tape (CT)
Data rate20MBd
Case6-SOIC (0.295\", 7.50mm Width)
Channels1
Inputs - side 1/Side 21/0
Rise (Fall time)5ns, 4ns
Propagation delay tpLH (tpHL)55ns, 55ns
Common mode transient immunity20kV/µs

Technical details

High-speed isolated digital link with reinforced barrier

The Toshiba TLP2766A(TP4,E is a single-channel, high-speed logic-output photocoupler rated for 20MBd data rate and 5000Vrms isolation voltage. The 20kV/µs minimum common-mode transient immunity ensures the output stays clean when switching noise couples across the barrier — a common failure point in motor drives and inverter-fed systems. Supply voltage spans 2.7V to 5.5V, so it interfaces directly with 3.3V or 5V logic without a level shifter.

Barrier rating and certification path

The 5000Vrms isolation rating in the 6-SOIC wide-body package (7.50mm width) supports reinforced isolation designs per IEC 60747-5-5 when the PCB layout provides at least 8mm creepage. ROHS3 compliance clears EU material restrictions for new product registrations.

Timing and drive margins for the bus

Propagation delay is 55ns max, symmetric between tpLH and tpHL, so pulse-width distortion stays within a few nanoseconds — important for isolated SPI clock or PWM duty-cycle accuracy. Rise/fall times are 5ns and 4ns typical, keeping edge rates fast enough for 20MBd NRZ data without excessive ringing. The 10mA per-channel output drive is sufficient for a single CMOS load; for fan-out to multiple gates, buffer externally.

The ROHS3 compliance is current and does not require a transition.

Package and footprint notes for layout

The surface-mount package requires no exposed pad; decoupling with a 0.1µF ceramic close to pins 5 and 8 (VCC and GND) is sufficient.

TLP2766A(TP4,E
[ALLOC] verified
Quote