7.5 ns propagation delay at 5 V — timing margin for 50 pF loads
The 74VHC02FT is a quad 2-input NOR gate from Toshiba's 74VHC series, a high-speed CMOS logic family that balances propagation delay against quiescent power. Each of the four independent gates accepts two inputs and outputs the NOR result — a logic LOW only when both inputs are HIGH. Output drive is symmetric at 8 mA source and sink, enough to switch the input of five 74VHC-family loads (standard fan-out of 10) or drive a low-speed LED indicator directly. The 2 µA max quiescent current keeps the idle draw negligible in battery-powered or always-on subsystems.
14-TSSOP footprint — board-fit for dense mixed-signal layouts
The 0.173-inch (4.40 mm) width keeps the package narrow enough to route between two 0.5 mm pitch BGA peripherals on a typical 8-layer board. The wide range means the gate's timing and drive specs hold across a cold start and a hot soak without derating. Input logic thresholds are 0.5 V (low) and 1.5 V (high) across the supply range — the 1 V noise margin at 3.3 V supply gives the gate immunity to ground bounce and coupled switching noise common on dense digital buses.
Active production — compliance and sourcing posture
Suitable for EU-market equipment without a RoHS waiver. No minimum order threshold beyond standard reel increments.