9 A peak drive — what it buys you on the bench
The UCC27322DR delivers 9 A peak source and 9 A peak sink current, enough to charge and discharge the gate capacitance of a large IGBT or paralleled MOSFET bank in the 20 ns typical rise and fall window. That 20 ns edge rate means the Miller plateau is traversed quickly — switching losses in the transistor stay low even at moderate frequencies, but the PCB loop inductance from the driver output to the gate resistor and back to the source kelvin connection must be kept under a few nH or the ringing will exceed the Vgs abs-max. The 4 V to 15 V supply range covers the standard bias rails for both logic-level and standard MOSFETs. At the low end, 4 V still gives enough headroom to fully enhance a logic-level FET; at 15 V the driver saturates a standard-gate transistor without exceeding the typical 20 V Vgs limit.
Logic interface and temperature grade
The non-inverting input means the output follows the input polarity — no inversion to account for in the control loop.